Programmable delay lines can be implemented using synchronous counters. In such a programmable delay line, an input trigger signal starts an oscillator or some other means of generating or gating a high speed clock signal, which is used to clock a synchronous counter. A digital comparator is used to generate the output signal when the counter reaches a predetermined value. The delay between the input signal and the output signal can be varied by changing the predetermined value that is compared to the counter output.
Many implementations of counter-controlled delay lines use synchronous counters to ensure that all of the counter output bits transition simultaneously, in order to offer the highest timing margin for the compare function. However, these implementations typically compromise between speed of operation, area, power consumption, and the width of the counter. For example, the counter needs to be as fast as possible in order to minimize the area needed for the oscillator. However, a fast counter may increase power consumption. Furthermore, the counter may need to be some number of bits wide to achieve the desired delay. However, the wide counter may consume a larger-than-desired area of the circuit. These and other concerns create problems in implementing counter-controlled delay lines.
The present invention may address one or more of the above issues.